Operation of an electronic system can include storage of data to a memory and retrieval of the data from the memory. Electronic memories can include an array of storage cells where each cell is capable of storing a bit of data. In such a memory, information can be placed "randomly" into, or taken out of, each storage element as required. This type of electronic memory is commonly referred to as a random access memory (RAM).
An advantage of RAM is that access time is the same for any bit in the matrix. In a shift register serial memory by comparison, access time depends on the position of the bit at the moment of access. A disadvantage of RAM as compared to read only memory (ROM), is that RAM is volatile, i.e. all stored information can be lost if a power supply fails. This is why data is often stored on auxiliary memory devices such as, e.g., disk or tape.
One type of RAM is a static random access memory (SRAM). SRAMs are favored where memory access times must be kept to a minimum. SRAMs also have relatively low power requirements and are commonly used in battery powered units, including portable computers.
Basically, an SRAM is an integrated circuit that stores data in a binary form (e.g., "1" or "0") in a number of cells. The basic storage cell in a RAM can be fabricated in metal oxide semiconductor (MOS) and bipolar transistor technologies. The most widely used RAMs use MOS transistors because they provide the highest component density and hence, more bits can be stored for a given chip size.
Metal oxide semiconductor (MOS) originally described transistor gates which were fabricated using metal over a thin oxide layer. AMOS transistor can also be commonly referred to as a field effect transistor (FET) or as a MOSFET. Today the term is applied more broadly to include transistors with gates of polysilicon over oxide. NMOS, PMOS and CMOS are three exemplary types of MOS technology. "NMOS" refers to n-type MOS transistors. "N-type" refers to a dopant introduced into silicon to enhance its ability to conduct electrons, which are negatively charged particles. "PMOS" uses a p-type dopant which enhances the conduction of electron "holes," which are positive charges. "CMOS" means complementary MOS and involves the fabrication of both PMOS and NMOS devices on a single substrate. Usually, PMOS devices are fabricated in n-type wells while NMOS devices are formed within primarily p-type substrate. NMOS has long prevailed over PMOS as a technology of choice, while CMOS has advanced rapidly as advantages of combining PMOS and NMOS have often outweighed the complexity of combining them. A PMOS can also be referred to as a PFET and an NMOS as an NFET.
Typically, the cells of an SRAM can be arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a complementary bit line pair that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
Specifically, memory cells can be arranged in a rectangular array to permit two dimensional addressing. A basic RAM can include the rectangular array of storage cells, two decoders, one each for addressing each of the dimensions of the array (i.e. the word lines and bit line pairs) of storage cells, write amplifiers for driving the memory, and sense amplifiers to detect (i.e. read) the stored digital information. For example, a 4096-word by 1-bit (4-kb.times.1) static RAM may illustratively include a 64 word line by 64 bit line pair two dimensional memory array, a 6-to-64 line column decoder, a 6-to-64 line row decoder, a write enable circuit, a sense circuit, and other control circuits.
To read data out of a cell, the output of a cell can be accessed by selecting the word line associated with the cell. In order to read, the write enable circuit can be grounded, i.e. set to 0. A complementary bit line pair can be connected to each cell in a given column. When the word line is activated for the selected cell, the logic level (i.e. 1 or 0) stored in the flip-flops or inverters of the selected cell can cause current to flow through the bit lines, setting the voltage on the bit line. A sense amplifier can detect and amplify the relative voltages on the bit lines in an output that indicates the contents of the selected cell. An input/output device for the array, such as a transistor, can pass the voltage on the bit lines for the selected cell or the output of a selected sense amplifier to an input/output pad for communication with another chip such as a processor of a computer or other electronic system associated with the SRAM. In a write operation, data can be passed from the input/output pads of the SRAM to the internal bit lines by the input/output device of the array for storage in the transistor flip-flops or inverters of the selected cell.
Memory devices can be used in satellites and in other computer equipment which can be placed in environments which are highly susceptible to radiation. For example, a memory cell in a satellite in a space environment, can be exposed to a radiation-induced soft error or single event upset (SEU) when a cell is struck by high energy particles. A soft error or single event upset typically is caused by electron-hole pairs created by, and along the path of, a single energetic particle as it passes through an integrated circuit such as a memory. Should the energetic particle generate the critical charge in the critical volume of a memory cell, then the logic state of the memory is upset. This critical charge, by definition, is the minimum amount of electrical charge required to change the logic state of the memory cell. The critical charge may also enter the memory through direct ionization from cosmic rays.
SEU typically results from alpha particles (helium nuclei), beta particles or gamma rays impacting a low-capacitance node of a semiconductor circuit. An example of a SEU of an inverter is illustratively described. An inverter includes a PMOS transistor and an NMOS transistor with their drains coupled and is used to generate complementary signals. When an alpha particle strikes bulk semiconductor material in the PMOS transistor, it generates electron-hole pairs. Assuming that the NMOS transistor is on and that the PMOS transistor is off, the holes which collect at the coupled drain can change the voltage at an output node coupled to the drains from a logic low to a logic high. Electrons will diffuse toward the circuit supply voltage through the PMOS. A charge generating energetic particle hit on the NMOS transistor has the opposite effect, with positive charges drifting towards ground and negative charges collecting at the drain output, thus possibly changing the logic state of the inverter with its NMOS transistor off and its PMOS transistor on. In P-substrate, bulk CMOS technologies with PMOS devices formed in an NWELL, the effect of a charge particle hitting an NMOS transistor diffusion is typically worse than when a charged particle hits a PMOS transistor diffusion in an NWELL.
As will be appreciated by those skilled in the art, when a heavy ion traverses a node within a memory storage cell, the ion can force the node from its original state to an opposite state for a period of time. This change of state can be due to the charge that the heavy ion deposits as it passes through the silicon of a MOS transistor of the memory cell. If this node is held in the opposite state for a period of time longer than the delay around a feedback loop of the memory cell, the cell can switch states and the stored data can be lost. The period of time which the node is held in its opposite state can depend on several factors including the charge deposited, the conductance of the transistors of the memory cell and the delay around the feedback loop of the memory cell.
Attempts have been made to radiation harden SRAM memory cells to reduce the susceptibility of cells to radiation induced upsets.
One way to prevent an SEU is to increase the conductance of transistors. In order to increase conductance, the size of the transistors must be increased. An increase in size of a memory cell by greater than ten times could be necessary. Such an increase would not be practical, since it is generally preferred that transistors be of minimal size in order to minimize the area of a memory cell.
A more economical solution can be to increase feedback delay. Increasing the feedback delay can give an "on" transistor, time to remove the deposited charge before the voltage state change can propagate sufficiently to establish regenerative feedback which could result in an upset. Feedback delay can be increased by adding resistors between the drains (or sources) and gates of the cell. These added resistors are commonly referred to as cross-coupled resistors.
Although cross-coupled resistors have proven effective in increasing the critical charge necessary to upset a memory cell, the resistors increase delay in the feedback loop to prevent a memory cell upset due to a heavy particle hit. Unfortunately, the resistors also resist a deliberate write and therefore can increase the write time of the memory cell. For a typical single event upset, write time can increase more than five times as compared to that without cross-coupled resistors.
In addition, cross-coupled resistors are often made using polysilicon with sheet resistance in a region where the temperature coefficient is negative and large. In a typical design, this temperature coefficient can cause write times to increase radically with decreases in temperature.
Another deficiency of conventional approaches, is that in order to gain immunity, radiation hardening of SRAM cells can reduce the rate of cell response. For example, when a particle strikes a node and deposits a charge, the cell can be too slow to respond and does not change state because a resistor in series with cross-coupled inverters can create an RC delay in combination with gate capacitance of the inverters.
This conventional approach has several deficiencies. Such a memory cell can require a resistor in series with cross coupled inverters. The resistor can be formed with a large resistance value and a close tolerance. Cell performance can be dominated by this resistance value, which can be difficult to control in the manufacturing process. As cell geometries go to ever smaller feature sizes (e.g., 0.5.mu. and below), gate capacitance can become so low that the resistance needed can be so large that it cannot be made to fit in a reasonably small area. Further, cell write performance can become slower, especially in cold temperature conditions if the resistor is implemented with a negative temperature coefficient.
It is desired that the present invention provide a radiation hardened SRAM cell which can easily be implemented using conventional complementary metal oxide semiconductor (CMOS) processes, and which has performance speed comparable to an SRAM cell that has not been radiation hardened.